Design Verification Engineer
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As a Design Verification Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design, physical design, and verification skills to integrate state of the art machine learning accelerators into custom SOCs, and contribute to power and performance optimization through power aware simulations, gate level simulations and performance simulations. You will work closely with SOC vendors, Validation teams, ML researchers, architects and designers in creating functional and physical integration requirements and test cases for multiple state of the art SOCs.
Design Verification Engineer Responsibilities
- Work with researchers and architects defining power and performance targets, and supporting power states and verification methodologies for the ML accelerator.
- Define and track detailed internal integration test plans for top-level design components, and SOC vendor test plans and use case testing.
- Drive gate-level simulation health for internal netlists and SOC vendor netlists.
- Implement scalable power aware simulation and gate level simulation infrastructure leveraging test benches in System Verilog.
- Keep track of power state coverage metrics and bugs encountered and fixed.
- Support post silicon bringup and debug activities.
- Collaborate with cross-functional teams such as Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
- Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.
Minimum Qualifications
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
- 10+ years of experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
- 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.
- Experience in EDA tools and Python scripting used to build tools and flows for verification environments.
- Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.
- Track record of 'first-pass success' in ASIC development cycles.
Preferred Qualifications
- Masters in Electrical Engineering or Computer Science.
- Experience in development of UVM based verification environments from scratch.
- Experience with low power design.
- Experience working with vendor, SOC teams and Validation teams.
- Experience mentoring other design verification engineers.
For those who live in or expect to work from California if hired for this position, please click here for additional information.
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About Meta
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
$173,000/year to $249,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
Equal Employment Opportunity and Affirmative Action
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here.
Meta is committed to providing reasonable support (called accommodations) in our recruiting processes for candidates with disabilities, long term conditions, mental health conditions or sincerely held religious beliefs, or who are neurodivergent or require pregnancy-related support. If you need support, please reach out to accommodations-ext@fb.com.
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