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ASIC Engineer, DFT

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ASIC Engineer, DFT
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Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test (DFT) methodologies, implementation, and verification to build best-in-class System on a Chip (SOC) and IP for data center applications. We are looking for individuals with strong background in Design for Testability (DFT) methodologies and implementation for IP/SOC, with a deep understanding of Siemens/Synopsys DFT EDA tools and IEEE standards (1149, 1500, 1687).
ASIC Engineer, DFT Responsibilities
  • Develop and implement DFT strategies for mixed-signal ICs, considering factors such as fault coverage, test time, and in-system test.
  • Proficiently use Siemens/Synopsys EDA tools for DFT-related tasks, including MBIST, scan insertion, and test pattern generation.
  • Ensure compliance with IEEE standards (1149, 1687) for DFT methodologies and test patterns.
  • Conduct fault simulation and coverage analysis to assess the effectiveness of DFT strategies and identify areas for improvement.
  • Generate high-quality test patterns using automated test pattern generation (ATPG) tools.
  • Verify the correctness of DFT implementation through simulation and hardware testing.
  • Collaborate with design/implementation teams to ensure that DFT requirements are met throughout the process.
Minimum Qualifications
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
  • 8+ years of experience in DFT for mixed-signal ICs.
  • Understanding of DFT concepts, including scan insertion, BIST, and boundary scan.
  • In-depth knowledge of DFT EDA tools (Siemens/Synopsys).
  • Familiarity with IEEE standards 1149, 1500, and 1687.
  • Experience with fault simulation and coverage analysis tools.
  • Knowledge of scripting languages (e.g., Perl, Python) for automation.
Preferred Qualifications
  • Master's degree in Electrical Engineering or Computer Engineering.
  • Experience with mixed-signal DFT methodologies, at IP subsystem, SOC, or disaggregated SOCs (2.5D or 3D).
  • Experience with hardware testing and debugging.
For those who live in or expect to work from California if hired for this position, please click here for additional information.
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$173,000/year to $249,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
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