Manage an ASIC design team responsible for various processing blocks in a SOC. Drive RTL design planning and execution, innovative design methodology development, IP design and SOC integration. Participate in silicon architecture, micro-architecture development, interface with Architecture, SW/FW, Verification, Modelling, Emulation, and Post-Silicon Validation teams.
Asic Design Engineering Manager Responsibilities
- Manage an ASIC design team responsible for various processing blocks in a SOC. Drive RTL design planning and execution, innovative design methodology development, u-Arch, IP design and SOC integration. Participate in silicon architecture, interface with Architecture, SW/FW, Design, Modelling, Emulation, and Post-Silicon Validation teams
- Partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, capacity planners and supply chain experts
- Contribute to and drive development of and maintain overall silicon strategy aligned to corporation's Long Range Plan objectives
- Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection and IP licensing
- Build, lead, and support a team of ASIC engineers through strategic hiring, training, and guidance to drive on-time and on-budget product delivery
- Contribute to, analyze, review SOWs from vendors, supporting documentation, requirements sets that meet the needs of internal customers
- Support engineering teams to define, debug, implement and deliver total solutions around purpose built ASICs
- Define, implement and maintain key performance indicators (KPI) for areas of responsibility
- Partner with technical program management and supply chain team members to manage external development partners, suppliers and vendors
Minimum Qualifications
- B.S. or M.S. degree in Computer Engineering or Electrical Engineering, relevant technical field, or equivalent practical experience
- 12+ years experience in ASIC/SoC RTL design
- 3+ years of experience as a People Manager
- Clear understanding of complexities involved with various RTL design tools, including Synopsys DC compiler, Cadence LEC, Spyglass.
- Track record of first-pass success in ASIC Development
- Experience working across multiple projects and adjusting priorities in partnership with stakeholders
- Experience with interpreting functional specs and creating comprehensive u-Arch
Preferred Qualifications
- Hands-on experience with complex subsystems like memory/LPDDR/HBM, cache, PCIE or Network on chip.
- In depth knowledge of at least one of these areas - NICs, signal processing algorithms, neural networks and machine learning concepts, and/or other neural network development framework
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