Analog Layout Engineer

Analog Layout Engineer
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Sunnyvale, CA
Join Meta's Wearable Silicon AMS team as an Analog Layout Engineer and play a key role in developing cutting-edge AMS IP's that enable the next generation of virtual and augmented reality systems. As an Analog IC Layout Engineer, you will work with a world-class group of engineers creating high performance and area/power efficient custom layouts in advanced CMOS process nodes for our next generation AR/VR products. You will work closely with circuit designers and the physical design team to define the IC floor-plan, chip partitioning and power distribution.
Analog Layout Engineer Responsibilities
  • Design and optimize complex layouts for mixed signal and analog circuits in deep sub-micron CMOS technologies
  • Collaborate with circuit designers to floor plan and complete layouts, ensuring seamless integration and optimal performance
  • Run physical design/reliability verification, debug and fix violations, ensuring the highest quality and reliability of our AMS IP's
  • Review and analyze layouts with circuit designers, providing expert feedback and guidance to ensure optimal design
  • Contribute to layout integration and final verification for tape out, ensuring a smooth and successful project delivery
Minimum Qualifications
  • Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
  • Bachelor's degree in Electrical Engineering, or relevant technical field, or equivalent practical experience
  • 3+ years of experience as an IC Layout Designer with analog/mixed signal layout experience
  • Proven experience with layout techniques for device matching, noise isolation, electro-migration, power distribution, latch-up and ESD circuits using state of the art nanometer process technologies
  • Proficiency with Cadence Virtuoso XL layout tool and Mentor Calibre physical design verification tools (DRC, LVS, ERC) or equivalent
  • Experience debugging and resolve LVS/DRC/ERC errors independently
Preferred Qualifications
  • Exposure to FinFET process technology and its constraints for analog layout techniques and qualities
  • Familiarity with Cadence Virtuoso advanced features, such as schematic and constraint driven layout, auto routing
  • Experience with Place and Route tools and scripting languages (perl, TCL, Python, or Cadence Skill)
  • Experience with memory layout
For those who live in or expect to work from California if hired for this position, please click here for additional information.
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About Meta
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

$106,000/year to $166,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.


Equal Employment Opportunity and Affirmative Action
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here.

Meta is committed to providing reasonable support (called accommodations) in our recruiting processes for candidates with disabilities, long term conditions, mental health conditions or sincerely held religious beliefs, or who are neurodivergent or require pregnancy-related support. If you need support, please reach out to accommodations-ext@fb.com.
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. We may use your information to maintain the safety and security of Meta, its employees, and others as required or permitted by law. You may view Meta Pay Transparency Policy, Equal Employment Opportunity is the Law notice, and Notice to Applicants for Employment and Employees by clicking on their corresponding links. Additionally, Meta participates in the E-Verify program in certain locations, as required by law.

Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may contact us at accommodations-ext@fb.com.