ASIC Engineer, Physical Design
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Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization. We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and high-performance designs to build efficient System on Chip (SoC) and IP for data center applications.
ASIC Engineer, Physical Design Responsibilities
- Develop and own physical design implementation of multi-hierarchy low-power and high-performance designs, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology nodes.
- Resolve design and flow issues related to the physical design, identify potential solutions, and drive execution.
- Deliver physical design of an end-to-end IP or integration of ASIC/SoC design and point out lower power and higher performance trade-offs.
- Define and implement schemes, including semi-custom placement and routing, to improve performance and power.
- Work with the RTL design team to understand partition architecture and drive physical aspects early in the design cycle.
- Interface with the RTL design team to drive design modifications to resolve congestion/timing issues and implement functional ECO’s.
- Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
- Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new vendor tools and functions.
Minimum Qualifications
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
- 4+ years of experience in interpersonal, teamwork, and communication skills and experience interfacing with cross-functional teams, IP, and EDA vendors.
- Experience in physical design and timing closure.
- Knowledge of RTL2GDSII flow and design tape-outs in 5nm or below process technologies.
- Experience with EDA tools like DC/Genus, Innovus/ICC2, Primetime, Redhawk/Voltus, or Calibre.
- Experience in floor planning, place & route, power and clock distribution, and timing convergence of high-frequency designs.
- Knowledge of geometry/process/device technology implications on physical design.
- Experience with large SOC designs (>20M gates) with frequencies over 1GHZ.
- Programming/scripting skills: TCL, Python, Perl or Shell.
Preferred Qualifications
- Experience in full chip floor planning, partitioning, budgeting, and power grid planning.
- Experience with low power implementation, power gating, multiple voltage rails, UPF/CPF knowledge.
- Experience in planning, implementing, and analyzing high-speed clock distribution networks. Experience with alternate strategies for clock distribution, including standard trees, mesh, H-Tree, and clock power reduction techniques.
- Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
- Knowledge of Circuit design, device physics, and deep sub-micron technology.
- Experience in the physical design of data-path intensive designs.
- Experience in the 3D-IC technology, methodology, and advanced packaging.
- Experience in validating Power Distribution Network (PDN), IR/EM, Thermals for 3D-IC.
For those who live in or expect to work from California if hired for this position, please click here for additional information.
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About Meta
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
$142,000/year to $203,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
Equal Employment Opportunity and Affirmative Action
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here.
Meta is committed to providing reasonable support (called accommodations) in our recruiting processes for candidates with disabilities, long term conditions, mental health conditions or sincerely held religious beliefs, or who are neurodivergent or require pregnancy-related support. If you need support, please reach out to accommodations-ext@fb.com.
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